CS7620 datasheet(11/70 Pages) CIRRUS

11 / 70 page

CS7620

DS301PP2

sets the black level value at the output of the ADC

to 64 in the 13 bit digital code. This loop is active

during the optically black pixels which are output

at the beginning and end of a frame as well as dur-

ing a portion of the horizontal blanking period. The

presence of black pixels in the CCD output is indi-

cated by the CLAMP pulse, which can either be

supplied externally or generated internally if the

timing for the CCD is generated by the CS7620.

The black level can also be written to through the

serial port.

In order to acquire a starting value for the black lev-

el, the loop will run over the several lines of black

pixels at the beginning of the frame. The block di-

agram of the loop is shown in Figure 10. The up-

date rate is once per line during active pixel lines,

and once every (n + 10) pixels during the optical

black lines.

CCD

INPUT

SIGNAL

Φ1

Φ2

OUT OF

STAGE 1

OUT OF

STAGE 2

OUT OF

STAGE 3

Figure 9. Idealized timing diagram of VGA/CDS circuit

V(1)

V(2)

V(3)

V(1)

V(2)

V(3)

V(1)

V(2)

V(3)

V(1)

V(2)

ADC

Z-1

DAC

BINARY

THERM

Z-1

FU = UPDATE FREQUENCY

FP = PIXEL FREQUENCY

CLIP

CDS/VGA

VIN

FROM SERIAL INTERFACE

BLK LVL LOOP

‘64’

Figure 10. Black level adjustment loop

GAIN REG

CS7620 bảng dữ liệu(PDF) 11 Page - Cirrus Logic

CS7620 bảng dữ liệu(HTML) 11 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

bảng dữ liệu tải về

Link URL