CS7620 datasheet(51/70 Pages) CIRRUS

51 / 70 page

CS7620

DS301PP2

4.33

Horizontal Timing Control - H4

Default = 1Eh; Read/Write (address 2Ch)

Bit Number

765432

Bit Name

Reserved

h4d

h4f_reg2

h4f_reg1

h4f_reg0

h4f_reg2

h4f_reg1

h4f_reg0

Default

0011110

Bit

Mnemonic

Function

Reserved

6h4d

During the vertical shift time, the horizontal clocks are held in one state. This

bit controls whether H4 is held high or low during this time.

A “0” indicates that the signal state is low, a “1” indicates that the signal state

is high.

h4f_reg2

The phase of the falling edge of H4 can be programmed through this register.

The falling edge of H4 corresponds to the rising edge of the internally selected

clock. The phases of these clocks in shown in Figure 19, with the complement-

ed clocks being the inverse of these (i.e. the falling edge of p1 is the rising

edge of p1, etc.).

0 = t0

1 = t1

2 = t2

3 = t3

4 = t4

5 = t5

6 = t6

7 = t7

(See Figure 19)

h4f_reg1

h4f_reg0

h4f_reg2

The phase of the rising edge of H4 can be programmed through this register.

The rising edge of H4 corresponds to the rising edge of the internally selected

clock. The phases of these clocks in shown are Figure 19, with the comple-

mented clocks being the inverse of these.

0 = t0

1 = t1

2 = t2

3 = t3

4 = t4

5 = t5

6 = t6

7 = t7

(See Figure 19)

h4f_reg1

h4f_reg0

CS7620 bảng dữ liệu(PDF) 51 Page - Cirrus Logic

CS7620 bảng dữ liệu(HTML) 51 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

bảng dữ liệu tải về

Link URL