CS7620 datasheet(52/70 Pages) CIRRUS

52 / 70 page

CS7620

DS301PP2

4.34

Horizontal Timing Control - Analog Delays

Default = 00h; Read/Write (address 2Dh)

Bit Number

765432

Bit Name

Resrved

phase_h1

phase_h0

rgf_reg1

rgf_reg0

rgr_reg1

rgr_reg0

Default

000000

Bit

Mnemonic

Function

7:6

Reserved

phase_h1

Phase Shift of H1-H4 Pulses: This register allows for minor shifts in the

phases of H1-H4. This can help to optimize the sampling time of the CCD in-

put signal. 1 unit of delay is ~1.5 ns. This should be used for final adjustments

only, with large adjustments done through the selection of the appropriate

clock phases for each edge. All four horizontal clocks shift together when this

0 - no shift

1 - 1.5 ns shift

2 - 3.0 ns shift

3 - 4.5 ns shift

phase_h0

rgf_reg1

RG Falling Edge Phase Shift: This register allows for minor shifts in the

phase of the falling edge of RG. 1 unit of delay is ~1.5 ns.

0 - no shift

1 - 1.5 ns shift

2 - 3.0 ns shift

3 - 4.5 ns shift

rgf_reg0

rgr_reg1

RG Rising Edge Phase Shift: This register allows for minor shifts in the

phase of the rising edge of RG. 1 unit of delay is ~1.5 ns.

0 - no shift

1 - 1.5 ns shift

2 - 3.0 ns shift

3 - 4.5 ns shift

rgr_reg0

CS7620 bảng dữ liệu(PDF) 52 Page - Cirrus Logic

CS7620 bảng dữ liệu(HTML) 52 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

bảng dữ liệu tải về

Link URL