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XRT75VL00D bảng dữ liệu(PDF) 43 Page - Exar Corporation |
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XRT75VL00D bảng dữ liệu(HTML) 43 Page - Exar Corporation |
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43 / 92 page ![]() XRT75VL00D REV. 1.0.3 E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER 38 0x01 R/W D0 DMOIE Writing a “1” to this bit field enables the DMO inter- rupt and triggers an interrupt when the transmitter driver fails. Writing a “0” disables the interrupt. 0 D1 RLOSIE Writing a “1” to this bit field enables the RLOS inter- rupt and triggers an interrupt when the RLOS condi- tion occurs. Writing a “0” disables the interrupt. 0 D2 RLOLIE Writing a “1” to this bit field enables the RLOL inter- rupt and triggers an interrupt when RLOL condition occurs. Writing a “0” disables the interrupt. 0 D3 FLIE Writing a “1” to this bit field enables the FL interrupt and triggers an interrupt when the FIFO Limit of the Jitter Attenuator is within 2 bits of overflow/underflow condition. Writing a “0” disables the interrupt. NOTE: This bit field is ignored when the Jitter Attenuator is disabled. 0 D4 PRBSIE Writing a “1” to this bit enables the PRBS bit error interrupt. 0 D5 CNT_SATIE Writing a “1” to this bit enables the PRBS error- counter saturation interrupt. When the PRBS error counter reaches 0xFFFF, an interrupt will be gener- ated. 0 0x02 Reset Upon Read D0 DMOIS This bit is set to “1” every time a DMO status change has occurred since the last cleared interrupt.This bit is cleared when read. 0 D1 RLOSIS This bit is set to “1” every time a RLOS status change has occurred since the last cleared interrupt. This bit is cleared when read. 0 D2 RLOLIS This bit is set to “1” every time a RLOL status change has occurred since the last cleared interrupt. This bit is cleared when read. 0 D3 FLIS This bit is set to “1” every time a FIFO Limit status change has occurred since the last cleared interrupt. This bit is cleared when read. 0 D4 PRBSIS This bit is set to “1” when a PRBS bit error is detected. This bit is cleared when read. 0 D5 CNT_SATIS This bit is set to “1” when the PRBS error counter has saturated (0xFFFF). This bit is cleared when read. 0 TABLE 16: REGISTER MAP DESCRIPTION ADDRESS (HEX) TYPE BIT LOCATION SYMBOL DESCRIPTION DEFAULT VALUE(BIN) |
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