XRT75VL00D datasheet(40/92 Pages) EXAR

40 / 92 page

XRT75VL00D

E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER

REV. 1.0.3

dejittered clock. When the FIFO is within two bits of overflowing or underflowing, the FIFO limit status bit, FL is

set to “1” in the Alarm status register. Reading this bit clears the FIFO and resets the bit into default state.

NOTE: It is recommended to select the 16-bit FIFO for delay-sensitive applications as well as for removing smaller amounts

of jitter.

Table 13 specifies the jitter transfer mask requirements for various data rates:

The jitter attenuator within the XRT75VL00D meets the latest jitter attenuation specifications and/or jitter

transfer characteristics as shown in the Figure 24.

7.0

SERIAL HOST INTERFACE:

A flexible serial microprocessor interface is incorporated in the XRT75VL00D. The interface is generic and is

designed to support the common microprocessors/microcontrollers. The XRT75VL00D operates in Host mode

when the HOST/HW pin is tied “High”. The serial interface includes a serial clock (SClk), serial data input

(SDI), serial data output (SDO), chip select (CS) and interrupt output (INT). The serial interface timing is shown

in Figure 11.

The active low interrupt output signal (INT pin) indicates alarm conditions like LOS, DMO and FL to the

processor.

TABLE 13: JITTER TRANSFER PASS MASKS

RATE

(KBITS)

MASK

(HZ)

(KHZ)

A1(dB)

A2(dB)

34368

G.823

ETSI-TBR-24

100

300

800K

0.5

-19.5

44736

GR-499, Cat I

GR-499, Cat II

GR-253 CORE

10k

56.6k

15k

300k

15k

0.1

51840

GR-253 CORE

40k

400k

0.1

FIGURE 24. JITTER TRANSFER REQUIREMENTS AND JITTER ATTENUATOR PERFORMANCE

J IT T E R F R E Q UE NCY (k Hz )

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