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86 / 400 page  &3, ,QWHUUXSW DQG 7UDS )XQFWLRQV User’s Manual 5-4 1999-08 The table below lists the vector locations for hardware traps and the corresponding status flags in register TFR. It also lists the priorities of trap service for cases, where more than one trap condition might be detected within the same instruction. After any reset (hardware reset, software reset instruction SRST, or reset by watchdog timer overflow) program execution starts at the reset vector at location 00’0000 H. Reset conditions have priority over every other system activity and therefore have the highest priority (trap priority III). Software traps may be initiated to any vector location between 00’0000 H and 00’01FCH. A service routine entered via a software TRAP instruction is always executed on the current CPU priority level which is indicated in bit field ILVL in register PSW. This means that routines entered via the software TRAP instruction can be interrupted by all hardware traps or higher level interrupt requests. Table 5-2 Hardware Trap Summary Exception Condition Trap Flag Trap Vector Vector Location Trap Number Trap Prio Reset Functions: Hardware Reset Software Reset Watchdog Timer Overflow RESET RESET RESET 00’0000 H 00’0000 H 00’0000 H 00 H 00 H 00 H III III III Class A Hardware Traps: Non-Maskable Interrupt Stack Overflow Stack Underflow NMI STKOF STKUF NMITRAP STOTRAP STUTRAP 00’0008 H 00’0010 H 00’0018 H 02 H 04 H 06 H II II II Class B Hardware Traps: Undefined Opcode Protected Instruction Fault Illegal Word Operand Access Illegal Instruction Access Illegal External Bus Access UNDOPC PRTFLT ILLOPA ILLINA ILLBUS BTRAP BTRAP BTRAP BTRAP BTRAP 00’0028 H 00’0028 H 00’0028 H 00’0028 H 00’0028 H 0A H 0A H 0A H 0A H 0A H I I I I I Reserved [2C H – 3CH][0BH – 0F H] Software Traps: TRAP Instruction Any [00’0000 H – 00’01FC H] in steps of 4 H Any [00 H – 7F H] Current CPU Priority |
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