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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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SAF-C161PI bảng dữ liệu(PDF) 55 Page - Infineon Technologies AG |
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SAF-C161PI bảng dữ liệu(HTML) 55 Page - Infineon Technologies AG |
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55 / 400 page  &3, 7KH &HQWUDO 3URFHVVLQJ 8QLW &38 User’s Manual 4-7 1999-08 4.2 Particular Pipeline Effects Since up to four different instructions are processed simultaneously, additional hardware has been spent in the C161PI to consider all causal dependencies which may exist on instructions in different pipeline stages without a loss of performance. This extra hardware (i.e. for ’forwarding’ operand read and write values) resolves most of the possible conflicts (e.g. multiple usage of buses) in a time optimized way and thus avoids that the pipeline becomes noticeable for the user in most cases. However, there are some very rare cases, where the circumstance that the C161PI is a pipelined machine requires attention by the programmer. In these cases the delays caused by pipeline conflicts can be used for other instructions in order to optimize performance. • Context Pointer Updating An instruction, which calculates a physical GPR operand address via the CP register, is mostly not capable of using a new CP value, which is to be updated by an immediately preceding instruction. Thus, to make sure that the new CP value is used, at least one instruction must be inserted between a CP-changing and a subsequent GPR-using instruction, as shown in the following example: I n :SCXT CP,#0FC00h ;select a new context I n+1 :.... ;must not be an instruction using a GPR I n+2 :MOV R0,#dataX ;write to GPR 0 in the new context • Data Page Pointer Updating An instruction, which calculates a physical operand address via a particular DPPn (n=0 to 3) register, is mostly not capable of using a new DPPn register value, which is to be updated by an immediately preceding instruction. Thus, to make sure that the new DPPn register value is used, at least one instruction must be inserted between a DPPn- changing instruction and a subsequent instruction which implicitly uses DPPn via a long or indirect addressing mode, as shown in the following example: I n :MOV DPP0,#4 ;select data page 4 via DPP0 I n+1 :.... ;must not be an instruction using DPP0 I n+2 :MOV DPP0:0000H,R1;move contents of R1 to address location 01’0000 H ;(in data page 4) supposed segment. is enabled |
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