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SAFC161PI bảng dữ liệu(PDF) 123 Page - Infineon Technologies AG

tên linh kiện SAFC161PI
Giải thích chi tiết về linh kiện  16-Bit Single-Chip Microcontroller
PDF  400 Pages
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nhà sản xuất  INFINEON [Infineon Technologies AG]
Trang chủ  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

SAFC161PI bảng dữ liệu(HTML) 123 Page - Infineon Technologies AG

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User’s Manual
6-7
1999-08
The table below lists the possible selections.
The PLL constantly synchronizes to the external clock signal. Due to the fact that the
external frequency is 1/F’th of the PLL output frequency the output frequency may be
slightly higher or lower than the desired frequency. This jitter is irrelevant for longer time
periods. For short periods (1...4 CPU clock cycles) it remains below 4%.
Figure 6-6
PLL Block Diagram
Table 6-1
C161PI Clock Generation Modes
P0.15-13
(P0H.7-5)
CPU Frequency
I
CPU = IOSC * F
External Clock
Input Range
1)
1)
The external clock input range refers to a CPU clock range of 10...25 MHz.
Notes
1 1 1
I
OSC * 4
2.5 to 6.25 MHz
Default configuration
1 1 0
I
OSC * 3
3.33 to 8.33 MHz
10 1
I
OSC * 2
5 to 12.5 MHz
1 0 0
I
OSC * 5
2 to 5 MHz
0 1 1
I
OSC * 1
1 to 25 MHz
Direct drive
2)
2)
The maximum frequency depends on the duty cycle of the external clock signal. In emulation mode pin P0.15
(P0H.7) is inverted, i.e. the configuration ’111’ would select direct drive in emulation mode.
0 1 0
I
OSC * 1.5
6.66 to 16.6 MHz
0 0 1
I
OSC / 2
2 to 50 MHz
CPU clock via prescaler
0 0 0
I
OSC * 2.5
4 to 10 MHz
PLL Circuit
f
PLL = F * fIN
reset
sleep
F
Reset
PWRDN
ISNC /
f
PLL
f
IN
f
CPU
lock
CLKCFG
(RP0H.7-5)
OWD
CLKCON
XP3INT



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