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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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SAFC161PI bảng dữ liệu(PDF) 33 Page - Infineon Technologies AG |
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SAFC161PI bảng dữ liệu(HTML) 33 Page - Infineon Technologies AG |
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33 / 400 page  &3, $UFKLWHFWXUDO2YHUYLHZ User’s Manual 2-17 1999-08 Parallel Ports The C161PI provides up to 76 IO lines which are organized into six input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The IO ports are true bidirectional ports which are switched to high impedance state when configured as inputs. The output drivers of three IO ports can be configured (pin by pin) for push/pull operation or open-drain operation via control registers. During the internal reset, all port pins are configured as inputs. All port lines have programmable alternate input or output functions associated with them. PORT0 and PORT1 may be used as address and data lines when accessing external memory, while Port 4 outputs the additional segment address bits A22/19/ 17...A16 in systems where segmentation is used to access more than 64 KBytes of memory. Port 6 provides I2C Bus lines and the chip select signals CS4...CS0. Port 2 accepts the fast external interrupt inputs. Port 3 includes alternate functions of timers, serial interfaces, the optional bus control signal BHE and the system clock output (CLKOUT). Port 5 is used for timer control signals and for the analog inputs to the A/D Converter. All port lines that are not used for these alternate functions may be used as general purpose IO lines. |
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