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88 / 400 page  &3, ,QWHUUXSW DQG 7UDS )XQFWLRQV User’s Manual 5-6 1999-08 The Interrupt Request Flag is set by hardware whenever a service request from the respective source occurs. It is cleared automatically upon entry into the interrupt service routine or upon a PEC service. In the case of PEC service the Interrupt Request flag remains set, if the COUNT field in register PECCx of the selected PEC channel decrements to zero. This allows a normal CPU interrupt to respond to a completed PEC block transfer. Note: Modifying the Interrupt Request flag via software causes the same effects as if it had been set or cleared by hardware. xxIC Interrupt Control Register (E)SFR (yyyy H/zzH) Reset value: - - 00 H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 xxIR xxIE ILVL GLVL - - - - - - - - rwh rw rw rw Bit Function GLVL Group Level Defines the internal order for simultaneous requests of the same priority. 3: Highest group priority 0: Lowest group priority ILVL Interrupt Priority Level Defines the priority level for the arbitration of requests. F H: Highest priority level 0 H: Lowest priority level xxIE Interrupt Enable Control Bit (individually enables/disables a specific source) 0: Interrupt request is disabled 1: Interrupt Request is enabled xxIR Interrupt Request Flag 0: No request pending 1: This source has raised an interrupt request |
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