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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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SAFC161PI bảng dữ liệu(PDF) 100 Page - Infineon Technologies AG |
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SAFC161PI bảng dữ liệu(HTML) 100 Page - Infineon Technologies AG |
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100 / 400 page  &3, ,QWHUUXSW DQG 7UDS )XQFWLRQV User’s Manual 5-18 1999-08 Context Switching An interrupt service routine usually saves all the registers it uses on the stack, and restores them before returning. The more registers a routine uses, the more time is wasted with saving and restoring. The C161PI allows to switch the complete bank of CPU registers (GPRs) with a single instruction, so the service routine executes within its own, separate context. The instruction “SCXT CP, #New_Bank” pushes the content of the context pointer (CP) on the system stack and loads CP with the immediate value “New_Bank”, which selects a new register bank. The service routine may now use its “own registers”. This register bank is preserved, when the service routine terminates, i.e. its contents are available on the next call. Before returning (RETI) the previous CP is simply POPped from the system stack, which returns the registers to the original bank. Note: The first instruction following the SCXT instruction must not use a GPR. Resources that are used by the interrupting program must eventually be saved and restored, e.g. the DPPs and the registers of the MUL/DIV unit. 5.5 Interrupt Response Times The interrupt response time defines the time from an interrupt request flag of an enabled interrupt source being set until the first instruction (I1) being fetched from the interrupt vector location. The basic interrupt response time for the C161PI is 3 instruction cycles. Figure 5-4 Pipeline Diagram for Interrupt Response Time Pipeline Stage Cycle 1 Cycle 2 Cycle 3 Cycle 4 FETCH N N + 1 N + 2 I1 DECODE N - 1 N TRAP (1) TRAP (2) EXECUTE N - 2 N - 1 N TRAP WRITEBACK N - 3 N - 2 N - 1 N Interrupt Response Time 1 0 IR-Flag |
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