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SAFC161PI bảng dữ liệu(PDF) 93 Page - Infineon Technologies AG |
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SAFC161PI bảng dữ liệu(HTML) 93 Page - Infineon Technologies AG |
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93 / 400 page  &3, ,QWHUUXSW DQG 7UDS )XQFWLRQV User’s Manual 5-11 1999-08 5.2 Operation of the PEC Channels The C161PI’s Peripheral Event Controller (PEC) provides 8 PEC service channels, which move a single byte or word between two locations in segment 0 (data pages 3...0). This is the fastest possible interrupt response and in many cases is sufficient to service the respective peripheral request (e.g. serial channels, etc.). Each channel is controlled by a dedicated PEC Channel Counter/Control register (PECCx) and a pair of pointers for source (SRCPx) and destination (DSTPx) of the data transfer. The PECC registers control the action that is performed by the respective PEC channel. PECCx PEC Ch.x Ctrl. Reg. SFR (FECy H/6zH, see table) Reset value: 0000 H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - INC BWT COUNT - --- - rw rw rw Bit Function COUNT PEC Transfer Count Counts PEC transfers and influences the channel’s action (see table below) BWT Byte / Word Transfer Selection 0: Transfer a Word 1: Transfer a Byte INC Increment Control (Modification of SRCPx or DSTPx) 0 0: Pointers are not modified 0 1: Increment DSTPx by 1 or 2 (BWT) 1 0: Increment SRCPx by 1 or 2 (BWT) 1 1: Reserved. Do not use this combination. (changed to ’10’ by hardware) Table 5-4 PEC Control Register Addresses Register Address Reg. Space Register Address Reg. Space PECC0 FEC0 H / 60H SFR PECC4 FEC8 H / 64H SFR PECC1 FEC2 H / 61H SFR PECC5 FECA H / 65H SFR PECC2 FEC4 H / 62H SFR PECC6 FECC H / 66H SFR PECC3 FEC6 H / 63H SFR PECC7 FECE H / 67H SFR |
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