HD64F2145 datasheet(302/829 Pages) RENESAS

tên linh kiện	HD64F2145

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302 / 829 page

Rev. 2.0, 08/02, page 262 of 788

11.7.2

Conflict between FRC Write and Increment

If an FRC increment pulse is generated during the state after an FRC write cycle, the write takes

priority and FRC is not incremented. Figure 11.18 shows the timing for this type of conflict.

Address

FRC address

Internal write

signal

FRC input

clock

Write data

FRC

Write cycle of FRC

Figure 11.18 FRC Write-Increment Conflict

11.7.3

Conflict between OCR Write and Compare-Match

If a compare-match occurs during the state after an OCRA or OCRB write cycle, the write takes

priority and the compare-match signal is disabled. Figure 11.19 shows the timing for this type of

conflict.

If automatic addition of OCRAR and OCRAF to OCRA is selected, and a compare-match occurs

in the cycle following the OCRA, OCRAR, and OCRAF write cycle, the OCRA, OCRAR and

OCRAF write takes priority and the compare-match signal is disabled. Consequently, the result of

the automatic addition is not written to OCRA. Figure 11.20 shows the timing for this type of

conflict.

HD64F2145 bảng dữ liệu(PDF) 302 Page - Renesas Technology Corp