HD64F2145 datasheet(173/829 Pages) RENESAS

173 / 829 page

Rev. 2.0, 08/02, page 133 of 788

6.7

Idle Cycle

When this LSI accesses the external address space, it can insert a 1-state idle cycle (T

I) between

bus cycles when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is

possible, for example, to avoid data collisions between ROM with a long output floating time, and

high-speed memory and I/O interfaces.

If an external write occurs after an external read while the ICIS0 bit is set to 1 in BCR, an idle

cycle is inserted at the start of the write cycle.

Figure 6.16 shows examples of idle cycle operation. In these examples, bus cycle A is a read cycle

for ROM with a long output floating time, and bus cycle B is a CPU write cycle. In figure 6.16 (a),

with no idle cycle inserted, a collision occurs in bus cycle B between the read data from ROM and

the CPU write data. In figure 6.16 (b), an idle cycle is inserted, thus preventing data collision.

Address bus

Bus cycle A

Data bus

Bus cycle B

Long output floating time

Data collision

(a) No idle cycle insertion

Address bus

Bus cycle A

Data bus

Bus cycle B

(b) Idle cycle insertion

Figure 6.16 Examples of Idle Cycle Operation

Table 6.5 shows the pin states in an idle cycle.

Table 6.5

Pin States in Idle Cycle

Pins

Pin State

A23 to A0,

,26

Contents of immediately following bus cycle

D15 to D0

High impedance

High

+:5, /:5

High

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