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HD64F2145 bảng dữ liệu(PDF) 171 Page - Renesas Technology Corp

tên linh kiện HD64F2145
Giải thích chi tiết về linh kiện  Hitachi 16-Bit Single-Chip Microcomputer
PDF  829 Pages
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nhà sản xuất  RENESAS [Renesas Technology Corp]
Trang chủ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD64F2145 bảng dữ liệu(HTML) 171 Page - Renesas Technology Corp

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Rev. 2.0, 08/02, page 131 of 788
By program wait
T
1
Address bus
Ø
/
(IOSE = 0)
Data bus
Read data
Read
,
Write data
Write
Note:
shown in Ø clock indicates the
pin sampling timing.
Data bus
T
2
T
W
T
W
T
W
T
3
By
pin
Figure 6.13 Example of Wait State Insertion Timing (Pin Wait Mode)
6.6
Burst ROM Interface
In this LSI, the external address space can be designated as the burst ROM space by setting the
BRSTRM bit in BCR to 1, and the burst ROM interface enabled. Consecutive burst accesses of a
maximum four or eight words can be performed only during CPU instruction fetch. 1 or 2 states
can be selected for burst ROM access.
6.6.1
Basic Operation Timing
The number of access states in the initial cycle (full access) of the burst ROM interface is
determined by the AST bit in WSCR. When the AST bit is set to 1, wait states can be inserted. 1
or 2 states can be selected for burst access according to the setting of the BRSTS1 bit in BCR.
Wait states cannot be inserted in a burst cycle. Burst accesses of a maximum four words is
performed when the BRSTS0 bit in BCR is cleared to 0, and burst accesses of a maximum eight
words is performed when the BRSTS0 bit in BCR is set to 1.
The basic access timing for the burst ROM space is shown in figures 6.14 and 6.15.



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