HD64F2145 datasheet(159/829 Pages) RENESAS

tên linh kiện	HD64F2145

Giải thích chi tiết về linh kiện	Hitachi 16-Bit Single-Chip Microcomputer

PDF	829 Pages

Scroll/Zoom	100%

nhà sản xuất	RENESAS [Renesas Technology Corp]

Trang chủ	http://www.renesas.com

Logo

159 / 829 page

Rev. 2.0, 08/02, page 119 of 788

RAME bit in SYSCR is set to 1, and disabled and specified as the external address space when the

RAME bit is cleared to 0.

6.4.4

I/O Select Signals

The LSI can output I/O select signals (

,26); the signal is driven low when the corresponding

external address space is accessed. Figure 6.2 shows an example of

,26 signal output timing.

Bus cycle

Address bus

External addresses selected by IOS

Figure 6.2

,26

,26 Signal Output Timing

Enabling or disabling

,26 signal output is performed by the IOSE bit in SYSCR. In extended

mode, the

,26 pin functions as an $6 pin by a reset. To use this pin as an ,26 pin, set the IOSE

bit to 1. For details, refer to section 8, I/O Ports.

The address ranges of the

,26 signal output can be specified by the IOS1 and IOS0 bits in BCR,

as shown in table 6.3.

Table 6.3

Address Range for

,26

,26 Signal Output

IOS1

IOS0

,26

,26 Signal Output Range

H'(FF)F000 to H'(FF)F03F

H'(FF)F000 to H'(FF)F0FF

H'(FF)F000 to H'(FF)F3FF

H'(FF)F000 to H'(FF)F7FF

(Initial value)

HD64F2145 bảng dữ liệu(PDF) 159 Page - Renesas Technology Corp