HD64F2145 datasheet(155/829 Pages) RENESAS

155 / 829 page

Rev. 2.0, 08/02, page 115 of 788

6.3.1

Bus Control Register (BCR)

BCR is used to specify the access mode for the external address space or the I/O area range when

the

$6/,26 pin is specified as an I/O strobe pin.

Bit

Bit Name

Initial Value

R/W

Description

7—

R/W

Reserved

This bit should not be written by 0.

ICIS0

R/W

Idle Cycle Insertion

Selects whether or not to insert 1-state of the idle

cycle between bus cycles when the external

write cycle follows the external read cycle.

0: Idle cycle not inserted when the external write

cycle follows the external read cycle

1: 1-state idle cycle inserted when the external

write cycle follows the external read cycle

BRSTRM

R/W

Burst ROM Enable

Selects the bus interface for the external address

space.

0: Basic bus interface

1: Burst ROM interface

BRSTS1

R/W

Burst Cycle Select 1

Selects the number of states in the burst cycle of

the burst ROM interface.

0: 1 state

1: 2 states

BRSTS0

R/W

Burst Cycle Select 0

Selects the number of words that can be

accessed by burst access via the burst ROM

interface.

0: Max, 4 words

1: Max, 8 words



0R/W

Reserved

This bit should not be written by 0.

IOS1

IOS0

R/W

IOS Select 1, 0

Select the address range where the

,26 signal is

output. For details, refer to table 6.3.

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