HD64F2145 datasheet(125/829 Pages) RENESAS

125 / 829 page

Rev. 2.0, 08/02, page 85 of 788

Section 5 Interrupt Controller

5.1

Features

• Two interrupt control modes

Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the

system control register (SYSCR).

• Priorities settable with ICR

An interrupt control register (ICR) is provided for setting interrupt priorities. Three priority

levels can be set for each module for all interrupts except NMI and address break.

• Independent vector addresses

All interrupt sources are assigned independent vector addresses, making it unnecessary for the

source to be identified in the interrupt handling routine.

• Thirty-one external interrupts

NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge

detection can be selected for NMI. Falling-edge, rising-edge, or both-edge detection, or level

sensing, can be selected for

,54: to ,543. The IRQ6 interrupt is shared by the interrupt from

the

,549 pin and eight external interrupt inputs (.,1: to .,13), and the IRQ7 interrupt is

shared by the interrupt from the

,54: pin and sixteen external interrupt inputs (.,148 to

.,1; and :8(: to :8(3). .,148 to .,13 and :8(: to :8(3 can be masked

individually by the user program.

• DTC control

The DTC can be activated by an interrupt request.

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