AD9929BBCZ datasheet(24/64 Pages) AD

24 / 64 page

AD9929

Rev. A | Page 24 of 64

As shown in Figure 17, the H2 output is the inverse of H1. The

internal propagation delay resulting from the signal inversion is

less than 1 ns, which is significantly less than the typical rise

time driving the CCD load. This results in a H1/H2 crossover

voltage at approximately 50% of the output swing. The

crossover voltage is not programmable.

NOTES

1. PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.

2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (

tCLIDLY = 6ns TYP).

P[0]

P[48] = P[0]

P[12]

P[24]

P[36]

1 PIXEL

PERIOD

CLI

tCLIDLY

POSITION

Figure 15. High Speed Clock Resolution from CLI Master Clock Input

CCD

SIGNAL

PROGRAMMABLE CLOCK POSITIONS

1. RG RISING EDGE (FIXED EDGE AT 000000)

2. RG FALLING EDGE (RGNEGLOC (ADDRESS 0x03))

3. SHP SAMPLE LOCATION (SHPLOC (ADDRESS 0x02))

4. SHD SAMPLE LOCATION (SHDLOC (ADDRESS 0x02))

5. H1 RISING EDGE LOCATION (H1POSLOC (ADDRESS 0x03))

6. H1 NEGATIVE EDGE LOCATION (FIXED AT (H1POSLOC + 24 STEPS))

7. H2 IS ALWAYS THE INVERSE OF H1

CDS

(INTERNAL)

Figure 16. High Speed Clock Programmable Locations

Table 15. RG, H1, SHP, SHD, DCLK, and DOUTPHASE Timing Parameters

Bit Width

Range

Description

RGNEGLOC1

Control (Address 0x03)

0 to 47 Edge Location

Falling Edge Location for RG

H1POSLOC1

Control (Address 0x03)

0 to 47 Edge Location

Positive Edge Location for H1

SHPLOC1

Control (Address 0x02)

0 to 47 Edge Location

Sample Location for SHP

SHDLOC1

Control (Address 0x02)

0 to 47 Edge Location

Sample Location for SHD

DOUTPHASE1

Control (Address 0x02)

0 to 47 Edge Location

Phase Location of Data Output [9:0]

DCLKPHASE

Control (Address 0x02)

0 to 47 Edge Location

Positive Edge of DCLK 1

1 The two MSB bits are used to select the quadrant

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