AD9929BBCZ datasheet(49/64 Pages) AD

49 / 64 page

AD9929

Rev. A | Page 49 of 64

XVSGLEN_0

XVSGACTLINE

NOTES

1. XVSGTOG_x (x = 0, 1) REFERENCES THE 13-BIT ST COUNTER

2. XVSGACTLINE (PROGRAMMABLE AT MODE_REG(1))

3. XVSGLEN (PROGRAMMABLE AT SYS_REG(14))

PROGRAMMABLE CLOCK POSITIONS

1. XVSGTOG_0 (PROGRAMMABLE AT SYS_REG(13))

2. XVSGTOG_1 (PROGRAMMABLE AT SYS_REG(13))

13-BIT

ST COUNTER

(FIXED)

XVSGTOG_0

XVSGLEN_1

XVSGTOG_1

Figure 55. Example of VSG Pulse

VSUB

SERIAL

WRITES

2 LINES

3 LINES

Figure 56. VSUB Timing Example

VSUB TIMING

The CCD readout bias (VSUB) can be programmed to accom-

modate different CCDs. VSUB on and off toggle positions and

polarity are controlled using VSUBTOG (Address 0x0D) and

VSUBPOL (Address 0x0D) registers, respectively, as described

in Table 36. Since the VSUBTOG is an 11-bit register, the VSUB

on position is programmable within any line. Figure 56 shows

an example of controlling VSUB using these registers.

Table 36. VSUB Registers

Name

Bit

Width

Type

Range

(Lines)

Description

VSUBPOL

Control

–

VSUBTOG

Control

0–2048

(0 = Low,

1 = High)

VSUB toggle

position

VSUB Placement and Polarity

Figure 56 shows the sequence of events for programming the

VSUB on and off toggle positions and polarity.

Program VSUBTOG = 2 and VSUBPOL = 1.

Since the VSUBTOG and VSUBPOL are VD synchronous

type registers, the falling edge of VD updates the serial

writes from Step 1.

VSUB is asserted high after two HD cycles.

Program VSUBTOG = 3 and VSUBPOL = 0.

Since the VSUBTOG and VSUBPOL are VD synchronous

type registers, the falling edge of VD updates the serial

writes from Step 4.

VSUB is asserted low after three HD cycles.

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