AD9929BBCZ datasheet(22/64 Pages) AD

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AD9929

Rev. A | Page 22 of 64

ANALOG FRONT END DESCRIPTION AND

OPERATION

The AD9929 AFE signal processing chain is shown in Figure 13.

Each processing step is essential in achieving a high quality

image from the raw CCD pixel data. Registers for the AD9929

AFE section are listed in Table 14.

Table 14. AFE Registers

Name

Bit

Width

Description

VGAGAIN

Control (Address 0x0E)

VGA Gain

REFBLACK

Control (Address 0x04)

Black Clamp

Level

AFESTBY

Control (Address 0x05)

AFE Standby

DC Restore

To reduce the large dc offset of the CCD output signal, a dc-

restore circuit is used with an external 0.1 µF series coupling

capacitor. This restores the dc level of the CCD signal to

approximately 1.5 V, to be compatible with the 3 V analog

supply of the AD9929.

Correlated Double Sampler

The CDS circuit samples each CCD pixel twice to extract the

video information and reject low frequency noise. The timing

shown in Figure 16 illustrates how the two internally generated

CDS clocks, SHP and SHD, are used to sample the reference and

data levels, respectively, of the CCD signal. The placement of the

SHP and SHD sampling edges is determined by the setting of

the SHPLOC (Address 0x02) and SHDLOC (Address 0x02)

registers. Placement of these two clock edges is critical in

achieving the best performance from the CCD.

6dB TO 40dB

CCDIN

DIGITAL

FILTER

CLPOB

DC RESTORE

OPTICAL BLACK

CLAMP

ADC

VGA

8-BIT

DAC

CLAMP LEVEL

VGA GAIN

CDS

INTERNAL

VREF

2V FULL

SCALE

PRECISION

TIMING

GENERATION

V-H

TIMING

GENERATION

SHP

SHD

1.5V

OUTPUT

DATA

LATCH

REFT

REFB

DOUT

PHASE

SHP

SHD

DOUT

PHASE

CLPOB

1.0V

2.0V

DOUT

1.0

µF

1.0

µF

0.1

µF

Figure 13. AFE Block Diagram

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