AD9929BBCZ datasheet(52/64 Pages) AD

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Giải thích chi tiết về linh kiện	CCD Signal Processor with Precision Timing Generator

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AD9929

Rev. A | Page 52 of 64

STROBE TIMING

The AD9929 provides a STROBE output pulse that can be used

to trigger the camera flash circuit. STROBE operation is set by

only one register, as described in Table 32. The STROBE output

is held low when STROBE_EN (Address 0x0B) is set to 0 and

enabled when set to 1. Providing STROBE_EN = 1, the STROBE

output pulse is asserted high on the rising edge of the last

XSUBCK pulse in the field, as shown in Figure 61. Also shown

in Figure 61, the STROBE pulse is asserted low again on the

rising edge of VSG.

XSUBCK

tEXP

XVSG1-

XVSG2

STROBE

SET STROBE_EN (ADDRESS 0x0B) = 1

NOTES

1. STROBE OUTPUT ASSERTED HIGH ON RISING EDGE OF LAST XSUBCK PULSE

2. STROBE OUTPUT ASSERTED LOW ON NEGATIVE EDGE OF XVSG PULSE

Figure 61. STROBE Output Timing

NOTES

1. INTERNAL 12-BIT H-GRAY CODE COUNTER IS RESET 7 CLOCK CYCLES AFTER THE HD FALLING EDGE.

CLI

0123

H-GRAY CODE

COUNTER

(PIXEL COUNTER)

3ns MIN

H-COUNTER

RESET

H-COUNTER

RESET

Figure 62. External VD/HD and Internal 12-Bit H-Gray Code Counter Synchronization, Slave Mode

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