GD5F1GQ4REFJS datasheet(43/60 Pages) GIGADEVICE

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SPI(x1/x2/x4) NAND Flash

13.3 Status Register and Driver Register

The NAND Flash device has an 8-bit status register that software can read during the device operation for operation state

query. The status register can be read by issuing the GET FEATURES (0FH) command, followed by the feature address

C0h or F0h (see FEATURE OPERATION). The Output Driver Register can be set and read by issuing the SET FEATURE

(0FH) and GET FEATURE command followed by the feature address D0h (see FEATURE OPERATION).

Table13-3. Status Register Bit Descriptions

Bit

Bit Name

Description

P_FAIL

Program

Fail

This bit indicates that a program failure has occurred (P_FAIL set to 1). It will also be

set if the user attempts to program an invalid address or a protected region, including

the OTP area. This bit is cleared during the PROGRAM EXECUTE command

sequence or a RESET command (P_FAIL = 0).

E_FAIL

Erase Fail

This bit indicates that an erase failure has occurred (E_FAIL set to 1). It will also be

set if the user attempts to erase a locked region. This bit is cleared (E_FAIL = 0) at the

start of the BLOCK ERASE command sequence or the RESET command.

WEL

Write

Enable

Latch

This bit indicates the current status of the write enable latch (WEL) and must be set

(WEL = 1), prior to issuing a PROGRAM EXECUTE or BLOCK ERASE command. It

is set by issuing the WRITE ENABLE command. WEL can also be disabled (WEL =

0), by issuing the WRITE DISABLE command.

OIP

Operation

In Progress

This bit is set (OIP = 1 ) when a PROGRAM EXECUTE, PAGE READ, BLOCK

ERASE, or RESET command is executing, indicating the device is busy. When the bit

is 0, the interface is in the ready state.

ECCS1,

ECCS0

ECCSE1

ECCSE0

ECC Status

ECCS provides ECC status as the following table.

ECCS and ECCSE are set to 00b either following a RESET, or at the beginning of the

READ. They are then updated after the device completes a valid READ operation.

ECCS and ECCSE are invalid if internal ECC is disabled (via a SET FEATURES

command to reset ECC_EN to 0).

After power-on RESET, ECC status is set to reflect the contents of block 0, page 0.

Table13-4. ECC Error Bits Descriptions

ECCS1

ECCS0

ECCSE1

ECCSE0

Description

No bit errors were detected during the previous read

algorithm.

Bit errors(<4) were detected and corrected.

Bit errors(=5) were detected and corrected.

Bit errors(=6) were detected and corrected.

Bit errors(=7) were detected and corrected.

Bit errors greater than ECC capability(8 bits) and not corrected

Bit errors reach ECC capability( 8 bits) and corrected

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