GD5F1GQ4REFJS datasheet(20/60 Pages) GIGADEVICE

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SPI(x1/x2/x4) NAND Flash

8.6 Read From Cache Dual IO (BBH)

The Read from Cache Dual I/O command (BBH) is similar to the Read form Cache x2 command (3BH) but with the

capability to input the 4 Dummy bits, followed by a 12-bit column address for the starting byte address and a dummy byte

by SIO0 and SIO1, each bit being latched in during the rising edge of SCLK, then the cache contents are shifted out 2-bit

per clock cycle from SIO0 and SIO1. The first address byte can be at any location. The address increments automatically

to the next higher address after each byte of data shifted out until the boundary wrap bit.Figure8-5. Read From Cache

Dual IO Sequence Diagram

Command

BBH

CS#

SCLK

SI(SIO0)

SO(SIO1)

9 10 11 12 13 14 15

16 17 18 19 20 21 22 23

A7-0

Dummy

Byte1

CS#

23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

SI(SIO0)

SO(SIO1)

SCLK

Byte2

Byte3

Byte4

Byte5

dummy<3:0>, A11-8

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