NUC505-YO2G datasheet(98/130 Pages) NUVOTON

98 / 130 page

NUC505

July. 26, 2018

Page 98 of 130

Rev.1.08

SPI Memory Interface Controller (SPIM)

6.13

6.13.1 Overview

The SPI Memory Interface Controller performs a serial-to-parallel conversion on data received

from the peripheral, and a parallel-to-serial conversion on data received from CPU. This controller

can drive up to 2 external peripherals (embedded SPI Flash or external SPI Flash) and act as a

SPI master. It can generate an interrupt signal when data transfer is finished and can be cleared

by writing 1 to the interrupt flag. The active level of device/slave select signal can be chosen to

low active or high active, which depends on the peripheral. Writing a divisor into the SPIM_CTL1

four 32-bit transmit/receive buffers, and can provide 1 to 4 burst mode operation. The number of

bits in each transaction can be 8, 16, 24, or 32; data can be transmitted/received up to four

successive transactions in one transfer.

6.13.2 Features



Supports SPI master mode



Supports DMA mode (DMA Write and DMA Read), Direct Memory Map (DMM) mode, and

I/O mode



8-, 16-, 24-, and 32-bit length of transaction



Supports standard (1-bit), dual (2-bit), and quad (4-bit) I/O transfer mode



Provides burst mode operation, which can transmit/receive data up to four successive

transactions in one transfer



Two slave/device select lines (embedded SPI Flash or external SPI Flash)



Fully static synchronous design with one clock domain

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