NUC505-YO2G datasheet(71/130 Pages) NUVOTON

tên linh kiện	NUC505-YO2G

Giải thích chi tiết về linh kiện	ARM짰 Cortex짰-M4 32-bit Microcontroller

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71 / 130 page

NUC505

July. 26, 2018

Page 71 of 130

Rev.1.08

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Debug access to all memory and registers in the system, including access to

memory mapped devices, access to internal core registers when the core is

halted, and access to debug control registers even while SYSRESETn is asserted.

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Serial Wire Debug Port (SW-DP) or Serial Wire JTAG Debug Port (SWJ-DP)

debug access. But NUC505 only supports SW-DP.

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Optional Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and

code patches.

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Optional Data Watchpoint and Trace (DWT) unit for implementing watchpoints,

data tracing, and system profiling.

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 Bus interfaces:

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Three Advanced High-performance Bus-Lite (AHB-Lite) interfaces: ICode, Dcode,

and System bus interfaces.

Private Peripheral Bus (PPB) based on Advanced Peripheral Bus (APB) interface.

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Bit-band support that includes atomic bit-band write and read operations.

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Memory access alignment.

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Write buffer for buffering of write data.

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Exclusive access transfers for multiprocessor systems.

NUC505-YO2G bảng dữ liệu(PDF) 71 Page - Nuvoton Technology Corporation