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MMPF0100Z bảng dữ liệu(PDF) 101 Page - NXP Semiconductors

tên linh kiện MMPF0100Z
Giải thích chi tiết về linh kiện  14 channel configurable power management integrated circuit
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MMPF0100Z bảng dữ liệu(HTML) 101 Page - NXP Semiconductors

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NXP Semiconductors
101
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.5.5
Specific registers
6.5.5.1
IC and version identification
The IC and other version details can be read via identification bits. These are hard-wired on chip and described in Tables 128 to 130.
6.5.5.2
Embedded memory
There are four register banks of general purpose embedded memory to store critical data. The data written to MEMA[7:0], MEMB[7:0],
MEMC[7:0], and MEMD[7:0] is maintained by the coin cell when the main battery is deeply discharged, removed, or contact-bounced. The
contents of the embedded memory are reset by COINPORB. The banks can be used for any system need for bit retention with coin cell
backup.
Table 128. Register DEVICEID - ADDR 0x00
Name
Bit #
R/W
Default
Description
DEVICEID
3:0
R
0x00
Die version.
0000 = PF0100
UNUSED
7:4
–
0x01
Unused
Table 129. Register SILICON REV- ADDR 0x03
Name
Bit #
R/W
Default
Description
METAL_LAYER_REV
3:0
R
0x00
Represents the metal mask revision
Pass 0.0 = 0000
.
.
Pass 0.15 = 1111
FULL_LAYER_REV
7:4
R
0x01
Represents the full mask revision
Pass 1.0 = 0001
.
.
Pass 15.0 = 1111
Table 130. Register FABID - ADDR 0x04
Name
Bit #
R/W
Default
Description
FIN
1:0
R
0x00
Allows for characterizing different options within
the same reticule
FAB
3:2
R
0x00
Represents the wafer manufacturing facility
Unused
7:0
R
0x00
unused
Table 131. Register MEMA ADDR 0x1C
Name
Bit #
R/W
Default
Description
MEMA
7:0
R/W
0
Memory bank A
Table 132. Register MEMB ADDR 0x1D
Name
Bit #
R/W
Default
Description
MEMB
7:0
R/W
0
Memory bank B



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