MMPF0100Z datasheet(77/128 Pages) NXP

77 / 128 page

NXP Semiconductors

PF0100Z

FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

6.4.6.3

LDO regulator control

Each LDO is fully controlled through its respective VGENxCTL register. This register enables the user to set the LDO output voltage

according to Table 91 for VGEN1 and VGEN2; and uses the voltage set point on Table 92 for VGEN3 through VGEN6.

Besides the output voltage configuration, the LDOs can be enabled or disabled at anytime during normal mode operation, as well as be

programmed to stay “ON” or be disabled when the PMIC enters standby mode. Each regulator has associated I2C bits for this. Table 93

presents a summary of all valid combinations of the control bits on VGENxCTL register and the expected behavior of the LDO output.

Table 91. VGEN1, VGEN2 output voltage configuration

Set point

VGENx[3:0]

VGENx output (V)

0000

0.800

0001

0.850

0010

0.900

0011

0.950

0100

1.000

0101

1.050

0110

1.100

0111

1.150

1000

1.200

1001

1.250

1010

1.300

1011

1.350

1100

1.400

1101

1.450

1110

1.500

1111

1.550

Table 92. VGEN3/ 4/ 5/ 6 output voltage configuration

Set point

VGENx[3:0]

VGENx output (V)

0000

1.80

0001

1.90

0010

2.00

0011

2.10

0100

2.20

0101

2.30

0110

2.40

0111

2.50

1000

2.60

1001

2.70

1010

2.80

1011

2.90

1100

3.00

1101

3.10

1110

3.20

1111

3.30

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