ZL2103ALAF datasheet(25/28 Pages) RENESAS

25 / 28 page

ZL2103

FN6966 Rev 5.00

Page 25 of 28

May 3, 2011

Phase Spreading

When multiple point of load converters share a common DC

input supply, it is desirable to adjust the clock phase offset of

each device such that not all devices start to switch

simultaneously. Setting each converter to start its switching cycle

at a different point in time can dramatically reduce input

capacitance requirements and efficiency losses. Since the peak

current drawn from the input supply is effectively spread out over

a period of time, the peak current drawn at any given moment is

reduced and the power losses proportional to the IRMS2 are

reduced dramatically.

In order to enable phase spreading, all converters must be

synchronized to the same switching clock. The CFG pin is used to

set the configuration of the SYNC pin for each device as

described in “Switching Frequency and PLL” on page 16.

Selecting the phase offset for the device is accomplished by

selecting a device address according to the following equation:

Phase offset = device address x 45°

For example:

• A device address of 0x00 or 0x20 would configure no phase

offset

• A device address of 0x01 or 0x21 would configure 45° of

phase offset

• A device address of 0x02 or 0x22 would configure 90° of

phase offset

The phase offset of each device may also be set to any value

between 0° and 360° in 22.5° increments via the I2C/SMBus

interface. Refer to Application Note AN2033 for further details.

Output Sequencing

A group of Zilker Labs devices may be configured to power up in

a predetermined sequence. This feature is especially useful when

powering advanced processors, FPGAs, and ASICs that require

one supply to reach its operating voltage prior to another supply

reaching its operating voltage in order to avoid latch-up from

occurring. Multi-device sequencing can be achieved by

configuring each device through the I2C/SMBus interface or by

using Zilker Labs patented autonomous sequencing mode.

Autonomous sequencing mode configures sequencing by using

events transmitted between devices over the DDC bus.

The sequencing order is determined using each device’s SMBus

address. Using autonomous sequencing mode (configured using

the CFG pin), the devices must be assigned sequential SMBus

addresses with no missing addresses in the chain. This mode will

also constrain each device to have a phase offset according to its

SMBus address as described in section “Phase Spreading” on

page 25.

The sequencing group will turn on in order starting with the

device with the lowest SMBus address and will continue through

to turn on each device in the address chain until all devices

connected have been turned on. When turning off, the device

with the highest SMBus address will turn off first followed in

reverse order by the other devices in the group.

Sequencing is configured by connecting a resistor from the CFG

pin to ground as described in Table 16. The CFG pin is also used

to set the configuration of the SYNC pin as well as to determine

the sequencing method and order. Please refer to section

“Switching Frequency and PLL” on page 16 for more details on

the operating parameters of the SYNC pin.

Multiple device sequencing may also be achieved by issuing

PMBus commands to assign the preceding device in the

sequencing chain as well as the device that will follow in the

sequencing chain. This method places fewer restrictions on the

SMBus address (no need of sequential address) and also allows

the user to assign any phase offset to any device irrespective of

its SMBus device address.

The Enable pins of all devices in a sequencing group must be tied

together and driven high to initiate a sequenced turn-on of the

group. Enable must be driven low to initiate a sequenced turnoff

of the group. Please refer to Application Note AN2033 for details

on sequencing via the I2C/SMBus interface.

TABLE 16. CFG PIN CONFIGURATIONS FOR SEQUENCING AND

TRACKING

RCFG

SYNC PIN

CONFIGURATION

SEQUENCING CONFIGURATION

Low

Input

Sequencing and Tracking are

disabled.

Open

Auto detect

High

Output

10k



Input

Sequencing and Tracking are

disabled.

11k



Auto detect

12.1k



Output

14.7k



Input

Device is FIRST in nested

sequence. Tracking disabled.

16.2k



Auto detect

17.8k



Output

21.5k



Input

Device is LAST in nested

sequence. Tracking disabled.

23.7k



Auto detect

26.1k



Output

31.6k



Input

Device is MIDDLE in nested

sequence. Tracking disabled.

34.8k



Auto detect

38.3k



Output

46.4k



Input

Sequence disabled. Tracking

enabled as defined in Table 13.

51.1k



Auto detect

56.2k



Output

ZL2103ALAF bảng dữ liệu(PDF) 25 Page - Renesas Technology Corp

ZL2103ALAF bảng dữ liệu(HTML) 25 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

bảng dữ liệu tải về

Link URL