ZL2103ALAF datasheet(16/28 Pages) RENESAS

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ZL2103

FN6966 Rev 5.00

Page 16 of 28

May 3, 2011

Power-good (PG)

The ZL2103 provides a Power-good (PG) signal that indicates the

output voltage is within a specified tolerance of its target level

and no fault condition exists. By default, the PG pin will assert if

the output is within +15%/-10% of the target voltage. These

limits may be changed via the I2C/SMBus interface. See

Application Note AN2033 for details.

A PG delay period is the time from when all conditions for

asserting PG are met and when the PG pin is actually asserted.

This feature is commonly used instead of an external reset

controller to signal the power supply is at its target voltage prior

to enabling any powered circuitry. By default, the ZL2103 PG

delay is set to 1ms and may be changed using the I2C/SMBus

interface as described in AN2033.

Switching Frequency and PLL

The ZL2103 incorporates an internal phase-locked loop (PLL) to

clock the internal circuitry. The PLL can be driven by an external

clock source connected to the SYNC pin. When using the internal

oscillator, the SYNC pin can be configured as a clock source for

other Zilker Labs devices.

The SYNC pin is a unique pin that can perform multiple functions

depending on how it is configured. The CFG pin is used to select

the operating mode of the SYNC pin as shown in Table 4.

Figure 15 illustrates the typical connections for each mode.

CONFIGURATION A: SYNC OUTPUT

When the SYNC pin is configured as an output (CFG pin is tied

HIGH), the device will run from its internal oscillator and will drive

the resulting internal oscillator signal (preset to 400kHz) onto the

SYNC pin so other devices can be synchronized to it. The SYNC

pin will not be checked for an incoming clock signal while in this

mode.

CONFIGURATION B: SYNC INPUT

When the SYNC pin is configured as an input (CFG pin is tied

LOW), the device will automatically check for an external clock

signal on the SYNC pin each time the EN pin is asserted. The

internal oscillator will then synchronize with the rising edge of the

external clock. The incoming clock signal must be in the range of

200kHz to 1MHz with a minimum duty cycle and must be stable

when the EN pin is asserted. The external clock signal must also

exhibit the necessary performance requirements (see the

“Electrical Specifications” table beginning on page 6).

TABLE 7. SYNC PIN FUNCTION SELECTION

CFG PIN

SYNC PIN FUNCTION

LOW

SYNC is configured as an input

OPEN

Auto detect mode

HIGH

SYNC is configured as an output fSW = 400kHz

ZL2103

Logic

High

SYNC

200kHz – 1MHz

ZL2103

SYNC

200kHz – 1MHz

ZL2103

N/C

SYNC

200kHz – 1MHz

A) SYNC = Output

B) SYNC = Input

ZL2103

N/C

SYNC

ZL2103

RSYNC

N/C

SYNC

Logic

High

Logic

Low

Open

C) SYNC = Auto Detect

FIGURE 15. SYNC PIN CONFIGURATIONS

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