ZL2103ALAF datasheet(2/28 Pages) RENESAS

2 / 28 page

ZL2103

FN6966 Rev 5.00

Page 2 of 28

May 3, 2011

Typical Application Circuit

The following application circuit represents a typical

implementation of the ZL2103. For PMBus operation, it is

recommended to tie the enable pin (EN) to SGND.

Block Diagram

VOUT

3.3V

VIN

12V

I2C/

SMBus††

DDC Bus†

ENABLE

47nF

C25

10µF

CDD

2.2µF

COUT

150µF

LOUT

2.2µH

CIN

100µF

VSET

SCL

SDA

SALRT

SYNC

DGND

ZL2103

PGND

VDDP

BST

PGOOD

CRA

4.7µF

F.B.

‡

Notes:

‡ Ferrite bead is optional for input noise suppression.

† The DDC bus pull-up resistance will vary based on the capacitive loading of the bus, including the number of devices

connected. The 10 k

 default value, assuming a maximum of 100 pF per device, provides the necessary 1 µs pull-up rise

time. Please refer to the Digital-DC Bus section for more details.

†† The I2C/SMBus pull-up resistance will vary based on the capacitive loading of the bus, including the number of devices

connected. Please refer to the I2C/SMBus specifications for more details.

FIGURE 2. 12V TO 3.3V/3A APPLICATION CIRCUIT (5ms SS DELAY, 5ms SS RAMP)



2.5V

LDO

PWM

Control

Drivers

BST

VSEN

VSET

VTRK

CFG

LDO

SMBus

NVM

Power

Mgmt

DDC Bus

DDC

VOUT

MGN

VIN

LDO

FIGURE 3. BLOCK DIAGRAM

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