ZL2103ALAF datasheet(18/28 Pages) RENESAS

18 / 28 page

ZL2103

FN6966 Rev 5.00

Page 18 of 28

May 3, 2011

small output filter made possible by a higher switching frequency

and getting better power supply efficiency. Size can be decreased

by increasing the switching frequency at the expense of

efficiency. Cost can be minimized by using through-hole

inductors and capacitors; however these components are

physically large.

To start the design, select a frequency based on Table 11. This

frequency is a starting point and may be adjusted as the design

progresses.

INDUCTOR SELECTION

The output inductor selection process must include several

trade-offs. A high inductance value will result in a low ripple

current (Iopp), which will reduce output capacitance and produce

a low output ripple voltage, but may also compromise output

transient load performance. Therefore, a balance must be struck

between output ripple and optimal load transient performance. A

good starting point is to select the output inductor ripple equal to

the expected load transient step magnitude (Iostep):

Now the output inductance can be calculated using Equation 3,

where VINM is the maximum input voltage:

The average inductor current is equal to the maximum output

current. The peak inductor current (ILpk) is calculated using

Equation 4 where IOUT is the maximum output current:

Select an inductor rated for the average DC current with a peak

current rating above the peak current computed in Equation 4.

In overcurrent or short-circuit conditions, the inductor may have

currents greater than 2X the normal maximum rated output

current. It is desirable to use an inductor that still provides some

inductance to protect the load and the internal MOSFETs from

damaging currents in this situation.

Once an inductor is selected, the DCR and core losses in the

inductor are calculated. Use the DCR specified in the inductor

manufacturer’s data sheet.

ILrms is given by Equation 6:

where IOUT is the maximum output current. Next, calculate the

core loss of the selected inductor. Since this calculation is

specific to each inductor and manufacturer, refer to the chosen

inductor data sheet. Add the core loss and the DCR loss and

compare the total loss to the maximum power dissipation

recommendation in the inductor data sheet.

OUTPUT CAPACITOR SELECTION

Several trade-offs must also be considered when selecting an

output capacitor. Low ESR values are needed to have a small

output deviation during transient load steps (Vosag) and low

output voltage ripple (Vorip). However, capacitors with low ESR,

such as semi-stable (X5R and X7R) dielectric ceramic capacitors,

also have relatively low capacitance values. Many designs can

use a combination of high capacitance devices and low ESR

devices in parallel.

For high ripple currents, a low capacitance value can cause a

significant amount of output voltage ripple. Likewise, in high

transient load steps, a relatively large amount of capacitance is

needed to minimize the output voltage deviation while the

inductor current ramps up or down to the new steady state

output current value.

As a starting point, apportion one-half of the output ripple

voltage to the capacitor ESR and the other half to capacitance, as

shown in Equations 7 and 8:

Use these values to make an initial capacitor selection, using a

single capacitor or several capacitors in parallel.

After a capacitor has been selected, the resulting output voltage

ripple can be calculated using Equation 9:

Because each part of this equation was made to be less than or

equal to half of the allowed output ripple voltage, the Vorip should

be less than the desired maximum output ripple.

INPUT CAPACITOR

It is highly recommended that dedicated input capacitors be

used in any point-of-load design, even when the supply is

powered from a heavily filtered 5V or 12V “bulk” supply from an

off-line power supply. This is because of the high RMS ripple

current that is drawn by the buck converter topology. This ripple

(ICINrms) can be determined from Equation 10:

TABLE 11. CIRCUIT DESIGN CONSIDERATIONS

FREQUENCY RANGE

EFFICIENCY

CIRCUIT SIZE

200kHz to 400kHz

Highest

Larger

400kHz to 800kHz

Moderate

Smaller

800kHz to 1MHz

Lower

Smallest

ostep

opp



(EQ. 2)

opp

INM

OUT

fsw





















(EQ. 3)

opp

OUT

Lpk





(EQ. 4)

Lrms

LDCR

DCR





(EQ. 5)



opp

OUT

Lrms





(EQ. 6)

orip

opp

OUT





(EQ. 7)

opp

orip

ESR





(EQ. 8)

OUT

opp

orip

ESR









(EQ. 9)

)

(

OUT

CINrms







(EQ. 10)

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