CS43L36 datasheet(30/89 Pages) CIRRUS

30 / 89 page

DS1081F3

CS43L36

4.4 Clocking Architecture

If MCLKINT is sourced from the PLL, on-the-fly frequency changes to the source may cause the PLL to go out of phase

lock with the clock source. To reduce the risk of audible artifacts, it is recommended to mute the system first. Any

necessary configuration changes based on the new clock source frequency must occur before unmuting the system.

Figure 4-12. MCLK INT Source Switching

For proper internal Fs clocking, the INTERNAL_FS and MCLKDIV bits must be configured, as shown in Table 4-2.

Note: The control-port frequency is equal to the MCLKINT frequency.

4.4.3

Fractional-N PLL

The CS43L36 has an integrated fractional-N PLL to support the clocking requirements of the internal analog circuits and

converters. This PLL can be enabled or bypassed to suit system-clocking needs. The input reference clock for the PLL is

the ASP_SCLK input pin. The reference clock frequency must be between 2.8224 and 25 MHz.

The PLL can be configured for a wide range of combinations of SCLK and MCLKINT. PLL_REF_INV (see p. 66) can be

used to invert the PLL reference clock. Table 4-4 lists common settings.

Table 4-3. Determining FsINT

MCLKINT (MHz) MCLKDIV (see p. 64 INTERNAL_FS (see p. 60) Resulting FsINT (kHz)

11.2896

44.1

12.288

22.5792

44.1

24.576

Table 4-4. Common PLL Setting Examples

SCLK

(MHz)

MCLK_SRC_SEL

(see p. 64) 1

SCLK_PREDIV

(see p. 66) 2

PLL_DIV_INT

(see p. 72)

PLL_DIV_FRAC

(see p. 72) 2

PLL_MODE

(see p. 72)

PLL_DIVOUT

(see p. 72) 3

MCLKINT

(MHz)

PLL_CAL_RATIO

(see p. 72)

n [4]

1.024

0xAC

0x44 0000

0x10

11.2896

118

0xBB

0x80 0000

0x10

125

0xC0

0x00 0000

0x10

12.288

128

1.536

0x72

0xD8 0000

0x10

11.2896

118

0x7D

0x00 0000

0x10

125

0x80

0x00 0000

0x10

12.288

128

0x7D

0x00 0000

0x08

125

0x80

0x00 0000

0x08

24.576

128

2.048

0x56

0x22 0000

0x10

11.2896

0x5D

0xC0 0000

0x10

0x60

0x00 0000

0x10

12.288

2.8224

0x40

0x00 0000

0x10

11.2896

128

0x40

0x00 0000

0x08

22.5792

128

0x3C

0x36 1134

0x10

11.2896

120

0x40

0x00 0000

0x10

128

0x40

0x00 0000

0x10

12.288

131

0x40

0x00 0000

0x08

128

0x40

0x00 0000

0x08

24.576

131

3.072

0x39

0x6C 0000

0x10

11.2896

118

0x3E

0x80 0000

0x10

125

0x40

0x00 0000

0x10

12.288

128

0x3E

0x80 0000

0x08

125

0x40

0x00 0000

0x08

24.576

128

MCLK

Internal MCLK

Fractional-N PLL

0 = Div by 1

1 = Div by 2

0 = Div by 250

1 = Div by 256

FSINT

MCLK_SRC_SEL p. 64

MCLKDIV p. 64

INTERNAL_FS p. 60

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