| công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
CS43L36 bảng dữ liệu(PDF) 44 Page - Cirrus Logic |
|
|
|||||||||||||||||||||||||||||
CS43L36 bảng dữ liệu(HTML) 44 Page - Cirrus Logic |
|
44 / 89 page ![]() DS1081F3 44 CS43L36 4.9 Power-Supply Considerations The following describes the VP monitor behavior with respect to the voltage level: • If VP drops below 3.0 V, TIP_SENSE performance may be compromised. • If VP drops below 2.6 V, the VPMON_TRIP status bit is set (see p. 68). An interrupt is triggered if M_VPMON_ TRIP = 0 (see p. 71). This bit must be unmasked/enabled only if VP is above the detection-voltage threshold. It must be masked/disabled by default to eliminate erroneous interrupts while VP is ramping or is known to be below the threshold voltage. • A brown-out condition remains until VP returns to a voltage level above 3.0 V. • The VP monitor circuit becomes unreliable at VP levels below 2.4 V. • The VP monitor is intended to detect slow transitioning signals about the 2.6-V threshold. Pulses of short duration are filtered by the monitor and may not trigger at the 2.6-V threshold, but at a value much lower than expected. |
|
Link URL |
| Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Liên kết đến bảng dữ liệu | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |