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CS43L36 bảng dữ liệu(PDF) 63 Page - Cirrus Logic

tên linh kiện CS43L36
Giải thích chi tiết về linh kiện  Low-Power, High-Performance Audio DAC with Class H Headphone Drivers
PDF  89 Pages
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nhà sản xuất  CIRRUS [Cirrus Logic]
Trang chủ  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS43L36 bảng dữ liệu(HTML) 63 Page - Cirrus Logic

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DS1081F3
63
CS43L36
7.2 Power Down and Headset Detects
7.2.3
Power Down Control 3
Address 0x1103
R/W
76
54
3
2
1
0
—
VPMON_PDNB
—
Default
00
10
0
0
0
0
Bits
Name
Description
7:3
—
Reserved
2VPMON_
PDNB
VPMON power down. VP monitor is described in Section 4.9.1.
0 (Default) Power down VPMON.
1 Power up VPMON.
1:0
—
Reserved
7.2.4
Oscillator Switch Control
Address 0x1107
R/W
765
43
21
0
—
SCLK_PRESENT
Default
00
00
000
0
Bits
Name
Description
7:1
—
Reserved
0SCLK_
PRESENT
SCLK present. Used to select the internal MCLK source. See Section 4.4 for programming details.
0→1 transition starts switch from RCO to selected internal MCLK (SCLK must be running first).
1→0 transition starts switch from selected internal MCLK to RCO (SCLK must keep running during transition).
0 (Default) SCLK may be present, but the internal MCLK is sourced from the RCO.
1 SCLK is present and the internal MCLK is sourced from the SCLK pin.
7.2.5
Oscillator Switch Status
Address 0x1109
R/O
76
54
3
2
1
0
—
OSC_PDNB_STAT
OSC_SW_SEL_STAT
Default
00
00
0
1
x
x
Bits
Name
Description
7:3
—
Reserved
2OSC_
PDNB_STAT
RCO power-down status. Indicates the RCO power state. See Section 4.4 for programming details.
0 RCO powered down
1 (Default) RCO powered up
1:0
OSC_SW_
SEL_STAT
RCO switch status. Indicates the RCO oscillator switch status. See Section 4.4 for programming details.
00 In transition
01 (Default) RCO selected for internal MCLK
10–11Reserved
7.2.6
Tip Sense Control 1
Address 0x1113
R/W
7
6543210
TS_INV
—
TS_FALL_DBNCE_TIME
TS_RISE_DBNCE_TIME
Default
0
0011011
Bits
Name
Description
7
TS_INV
Tip sense raw signal invert. Used to invert the raw signal from the tip-sense circuit. Reverses the meaning of TS_
UNPLUG_DBNC and TS_PLUG_DBNC (see p. 64).
0 (Default) Not inverted
1 Inverted
6
—
Reserved
5:3
TS_FALL_
DBNCE_TIME
Tip sense falling debounce time. Section 4.8.3 gives programming details.
000 0 ms
001 125 ms
010 250 ms
011 (Default) 500 ms
100 750 ms
101 1.0 s
110 1.25 s
111 1.5 s
2:0
TS_RISE_
DBNCE_TIME
Tip sense rising debounce time. Section 4.8.3 gives programming details.
000 0 ms
001 125 ms
010 250 ms
011 (Default) 500 ms
100 750 ms
101 1.0 s
110 1.25 s
111 1.5 s



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