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MB96F348CWCPMC-GSE2 bảng dữ liệu(PDF) 100 Page - Cypress Semiconductor

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nhà sản xuất  CYPRESS [Cypress Semiconductor]
Trang chủ  http://www.cypress.com
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MB96F348CWCPMC-GSE2 bảng dữ liệu(HTML) 100 Page - Cypress Semiconductor

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MB96340 Series
Document Number: 002-04579 Rev. *A
Page 100 of 109
Timer mode
PLL
CLKMC = 4 MHz, CLKPLL = 56 MHz
(System clocks are stopped in this mode)
Regulator in High Power Mode, Core Voltage = 1.9 V
Main osc.
CLKMC = 4 MHz
(System clocks are stopped in this mode)
Regulator in High Power Mode, Core Voltage = 1.8 V
RC clock fast
CLKRC = 2 MHz
(System clocks are stopped in this mode)
Regulator in High Power Mode, Core Voltage = 1.8 V
RC clock slow
CLKRC = 100 kHz
(System clocks are stopped in this mode)
Regulator in High Power Mode, Core Voltage = 1.8 V
Sub osc.
CLKSC = 100 kHz
(System clocks are stopped in this mode)
Regulator in Low Power Mode A, Core Voltage = 1.8 V
Stop mode
stopped
(All clocks are stopped in this mode)
Regulator in Low Power Mode B, Core Voltage = 1.8 V
Table 6: Used settings
Mode
Selected Source
Clock
Clock/Regulator Settings



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