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MB96F348CWCPMC-GSE2 bảng dữ liệu(PDF) 99 Page - Cypress Semiconductor

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MB96F348CWCPMC-GSE2 bảng dữ liệu(HTML) 99 Page - Cypress Semiconductor

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MB96340 Series
Document Number: 002-04579 Rev. *A
Page 99 of 109
Table 6: Used settings
Mode
Selected Source
Clock
Clock/Regulator Settings
Run mode
PLL
CLKS1 = CLKS2 = CLKB = CLKP1 = 56 MHz
CLKP2 = 28 MHz
Regulator in High Power Mode
Core Voltage = 1.9 V
Main osc.
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 4 MHz
Regulator in High Power Mode
Core Voltage = 1.8 V
RC clock fast
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 2 MHz
Regulator in High Power Mode
Core Voltage = 1.8 V
RC clock slow
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 100 kHz
Regulator in High Power Mode
Core Voltage = 1.8 V
Sub osc.
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 32 kHz
Regulator in Low Power Mode A
Core Voltage = 1.8 V
Sleep mode
PLL
CLKS1 = CLKS2 = CLKP1 = 56 MHz
CLKP2 = 28 MHz
(CLKB is stopped in this mode)
Regulator in High Power Mode
Core Voltage = 1.9 V
Main osc.
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 4 MHz
(CLKB is stopped in this mode)
Regulator in High Power Mode
Core Voltage = 1.8 V
RC clock fast
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 2 MHz
(CLKB is stopped in this mode)
Regulator in High Power Mode
Core Voltage = 1.8 V
RC clock slow
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 100 kHz
(CLKB is stopped in this mode)
Regulator in High Power Mode
Core Voltage = 1.8 V
Sub osc.
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 32 kHz
(CLKB is stopped in this mode)
Regulator in Low Power Mode A
Core Voltage = 1.8 V



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