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MB91F467BA bảng dữ liệu(PDF) 114 Page - Cypress Semiconductor |
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MB91F467BA bảng dữ liệu(HTML) 114 Page - Cypress Semiconductor |
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114 / 127 page ![]() MB91460B Series Document Number: 002-04608 Rev. *A Page 113 of 126 15.7.4 I 2C AC Timings at VDD5 = 3.0 to 5.5 V ■ Conditions during AC measurements All AC tests were measured under the following conditions: ❐ -IOdrive = 3 mA ❐ -VDD5 = 3.0 V to 5.5 V, Iload = 3 mA ❐ -VSS5 = 0 V ❐ -Ta = - 40 °C to + 125 °C ❐ -Cl = 50 pF ❐ -VOL = 0.3 × VDD5 ❐ -VOH = 0.7 × VDD5 ❐ -EPILR = 0, PILR = 0 (CMOS Hysteresis 0.3 × VDD5/0.7 × VDD5) 15.7.4.1 Fast mode: (VDD5 3.5 V to 5.5 V, VSS5 AVSS5 0 V, TA 40 C to 125 C) 1. The noise filter will suppress single spikes with a pulse width of 0ns and between (1 to 1.5) cycles of peripheral clock, depending on the phase relationship between I2C signals (SDA, SCL) and peripheral clock. Note: tCLKP is the cycle time of the peripheral clock. Parameter Symbol Pin name Value Unit Remark Min Max SCL clock frequency fSCL SCLn 0 400 kHz Hold time (repeated) START condition. After this period, the first clock pulse is gen- erated tHD;STA SCLn, SDAn 0.6 s LOW period of the SCL clock tLOW SCLn 1.3 s HIGH period of the SCL clock tHIGH SCLn 0.6 s Setup time for a repeated START condition tSU;STA SCLn, SDAn 0.6 s Data hold time for I2C-bus devices tHD;DAT SCLn, SDAn 0 0.9 s Data setup time tSU;DAT SCLn SDAn 100 ns Rise time of both SDA and SCL signals tr SCLn, SDAn 20 + 0.1Cb 300 ns Fall time of both SDA and SCL signals tf SCLn, SDAn 20 + 0.1Cb 300 ns Setup time for STOP condition tSU;STO SCLn, SDAn 0.6 s Bus free time between a STOP and START condition tBUF SCLn, SDAn 1.3 s Capacitive load for each bus line Cb SCLn, SDAn 400 pF Pulse width of spike suppressed by input filter tSP SCLn, SDAn 0 (1..1.5) × tCLKP ns [1] |
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