MB91F467BA datasheet(112/127 Pages) CYPRESS

112 / 127 page

MB91460B Series

Document Number: 002-04608 Rev. *A

Page 111 of 126

15.7.3

LIN-USART Timings at VDD5 = 3.0 to 5.5 V

■ Conditions during AC measurements

■ All AC tests were measured under the following conditions:

❐ - IOdrive = 5 mA

❐ - VDD5 = 3.0 V to 5.5 V, Iload = 3 mA

❐ - VSS5 = 0 V

❐ - Ta = -40 C to +125× C

❐ - Cl = 50 pF (load capacity value of pins when testing)

❐ - VOL = 0.2 x VDD5

❐ - VOH = 0.8 x VDD5

❐ - EPILR = 0, PILR = 1 (Automotive Level = worst case)

(VDD5  3.0 V to 5.5 V, VSS5  AVSS5  0 V, TA  40 C to  125 C)

1. Parameter m depends on tSCYCI and can be calculated as :

■ if tSCYCI  2*k*tCLKP, then m  k, where k is an integer > 2

■ if tSCYCI  (2*k  1)*tCLKP, then m  k  1, where k is an integer > 1

Notes :

■ The above values are AC characteristics for CLK synchronous mode.

■ tCLKP is the cycle time of the peripheral clock.

Parameter

Symbol Pin name

Condition

VDD5  3.0 V to 4.5 V

VDD5  4.5 V to 5.5 V

Unit

Min

Max

Min

Max

Serial clock cycle time

tSCYCI

SCKn

Internal clock

operation

(master mode)

4 tCLKP

-4 tCLKP

-ns

SCK ↓ → SOT delay

time

tSLOVI

SCKn

SOTn

- 30

- 20

SOT → SCK ↓ delay

time

tOVSHI

SCKn

SOTn

m × tCLKP - 30[1]

-m × tCLKP - 20[1]

-ns

Valid SIN → SCK ↑

setup time

tIVSHI

SCKn

SINn

tCLKP + 55

tCLKP + 45

SCK ↑ → valid SIN

hold time

tSHIXI

SCKn

SINn

Serial clock “H” pulse

width

tSHSLE

SCKn

External clock

operation

(slave mode)

tCLKP + 10

Serial clock“L” pulse

width

tSLSHE

SCKn

tCLKP + 10

SCK ↓ → SOT delay

time

tSLOVE

SCKn

SOTn

-2 tCLKP + 55

2 tCLKP + 45

Valid SIN → SCK ↑

setup time

tIVSHE

SCKn

SINn

SCK ↑ → valid SIN

hold time

tSHIXE

SCKn

SINn

tCLKP + 10

SCK rising time

tFE

SCKn

SCK falling time

tRE

SCKn

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