PIC18F4539-ESLASHMLSQTP datasheet(222/322 Pages) MICROCHIP

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PIC18FXX39

DS30485A-page 220

Preliminary

 2002 Microchip Technology Inc.

BCF

Bit Clear f

Syntax:

[ label ] BCF

f,b[,a]

Operands:

≤ f ≤ 255

≤ b ≤ 7

∈ [0,1]

Operation:

→ f<b>

Status Affected:

None

Encoding:

1001

bbba

ffff

Description:

Bit 'b' in register 'f' is cleared. If ‘a’

is 0, the Access Bank will be

selected, overriding the BSR value.

If ‘a’ = 1, then the bank will be

selected as per the BSR value

(default).

Words:

Cycles:

Q Cycle Activity:

Decode

Read

Process

Data

Write

Example:

BCF

FLAG_REG,

7, 0

Before Instruction

FLAG_REG = 0xC7

After Instruction

FLAG_REG = 0x47

Branch if Negative

Syntax:

[ label ] BN n

Operands:

-128

≤ n ≤ 127

Operation:

if negative bit is ‘1’

(PC) + 2 + 2n

→ PC

Status Affected:

None

Encoding:

1110

0110

nnnn

Description:

If the Negative bit is ‘1’, then the

program will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC+2+2n. This instruction is then

a two-cycle instruction.

Words:

Cycles:

1(2)

Q Cycle Activity:

If Jump:

Decode

Read literal

'n'

Process

Data

Write to PC

operation

If No Jump:

Decode

Read literal

'n'

Process

Data

operation

Example:

HERE

Jump

Before Instruction

address (HERE)

After Instruction

If Negative

address (Jump)

If Negative

address (HERE+2)

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