PIC18F4539-ESLASHMLSQTP datasheet(76/322 Pages) MICROCHIP

76 / 322 page

PIC18FXX39

DS30485A-page 74

Preliminary

 2002 Microchip Technology Inc.

8.2

PIR Registers

The PIR registers contain the individual flag bits for the

peripheral interrupts. Due to the number of peripheral

interrupt sources, there are two Peripheral Interrupt

Flag registers (PIR1, PIR2).

PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1

Note 1: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>).

2: User software should ensure the appropri-

ate interrupt flag bits are cleared prior to

enabling an interrupt, and after servicing

that interrupt.

R/W-0

R-0

R/W-0

U-0

R/W-0

PSPIF(1)

ADIF

RCIF

TXIF

SSPIF

—TMR2IF(2)

TMR1IF

bit 7

bit 0

bit 7

PSPIF(1): Parallel Slave Port Read/Write Interrupt Flag bit

= A read or a write operation has taken place (must be cleared in software)

= No read or write has occurred

bit 6

ADIF: A/D Converter Interrupt Flag bit

= An A/D conversion completed (must be cleared in software)

= The A/D conversion is not complete

bit 5

RCIF: USART Receive Interrupt Flag bit

= The USART receive buffer, RCREG, is full (cleared when RCREG is read)

= The USART receive buffer is empty

bit 4

TXIF: USART Transmit Interrupt Flag bit (see Section 17.0 for details on TXIF functionality)

= The USART transmit buffer, TXREG, is empty (cleared when TXREG is written)

= The USART transmit buffer is full

bit 3

SSPIF: Master Synchronous Serial Port Interrupt Flag bit

= The transmission/reception is complete (must be cleared in software)

= Waiting to transmit/receive

bit 2

Unimplemented: Read as ‘0’

bit 1

TMR2IF(2): TMR2 to PR2 Match Interrupt Flag bit

= TMR2 to PR2 match occurred (must be cleared in software)

= No TMR2 to PR2 match occurred

bit 0

TMR1IF: TMR1 Overflow Interrupt Flag bit

= TMR1 register overflowed (must be cleared in software)

= MR1 register did not overflow

Note 1: This bit is reserved on PIC18F2X39 devices; always maintain this bit clear.

2: This bit is reserved for use by the ProMPT kernel; do not alter its value.

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

PIC18F4539-E/MLSQTP bảng dữ liệu(PDF) 76 Page - Microchip Technology

PIC18F4539-E/MLSQTP bảng dữ liệu(HTML) 76 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL