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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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HT67F5652 bảng dữ liệu(PDF) 112 Page - Holtek Semiconductor Inc |
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HT67F5652 bảng dữ liệu(HTML) 112 Page - Holtek Semiconductor Inc |
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112 / 224 page  Rev. 1.00 11� De�e��e� 0�� �01� Rev. 1.00 113 De�e��e� 0�� �01� HT67F5652 24-Bit Delta Sigma A/D + LCD Flash MCU HT67F5652 24-Bit Delta Sigma A/D + LCD Flash MCU Timer/Counter Mode Toselectthismode,bitsTnM1andTnM0intheSTMnC1registershouldbesetto11respectively. TheTimer/CounterModeoperatesinanidenticalwaytotheCompareMatchOutputMode generatingthesameinterruptflags.TheexceptionisthatintheTimer/CounterModetheTMoutput pinisnotused.ThereforetheabovedescriptionandTimingDiagramsfortheCompareMatch OutputModecanbeusedtounderstanditsfunction.AstheTMoutputpinisnotusedinthismode, thepincanbeusedasanormalI/Opinorotherpin-sharedfunction. PWM Output Mode Toselectthismode,bitsTnM1andTnM0intheSTMnC1registershouldbesetto10respectively andalsotheTnIO1andTnIO0bitsshouldbesetto10respectively.ThePWMfunctionwithin theTMisusefulforapplicationswhichrequirefunctionssuchasmotorcontrol,heatingcontrol, illuminationcontroletc.Byprovidingasignaloffixedfrequencybutofvaryingdutycycleonthe TMoutputpin,asquarewaveACwaveformcanbegeneratedwithvaryingequivalentDCRMS values. AsboththeperiodanddutycycleofthePWMwaveformcanbecontrolled,thechoiceofgenerated waveformisextremelyflexible.InthePWMOutputMode,theTnCCLRbithasnoeffectasthe PWMperiod.BothoftheCCRAandCCRPregistersareusedtogeneratethePWMwaveform,one registerisusedtocleartheinternalcounterandthuscontrolthePWMwaveformfrequency,while theotheroneisusedtocontrolthedutycycle.Whichregisterisusedtocontroleitherfrequency ordutycycleisdeterminedusingtheTnDPXbitintheSTMnC1register.ThePWMwaveform frequencyanddutycyclecanthereforebecontrolledbythevaluesintheCCRAandCCRPregisters. Aninterruptflag,oneforeachoftheCCRAandCCRP,willbegeneratedwhenacomparematch occursfromeitherComparatorAorComparatorP.TheTnOCbitintheSTMnC1registerisusedto selecttherequiredpolarityofthePWMwaveformwhilethetwoTnIO1andTnIO0bitsareusedto enablethePWMoutputortoforcetheTMoutputpintoafixedhighorlowlevel.TheTnPOLbitis usedtoreversethepolarityofthePWMoutputwaveform. 16-bit STM, PWM Output Mode, Edge-aligned Mode, TnDPX=0 CCRP 1~255 0 Pe�iod CCRP×�5� �553� Duty CCRA IffSYS=16MHz,TMclocksourceselectfSYS/4,CCRP=2andCCRA=128, TheSTMPWMoutputfrequency=(fSYS/4)/(2×256)=fSYS/2048=7.8125kHz,duty=128/(2×256) =25%. IftheDutyvaluedefinedbytheCCRAregisterisequaltoorgreaterthanthePeriodvalue,thenthe PWMoutputdutyis100%. 16-bit STM, PWM Output Mode, Edge-aligned Mode, TnDPX=1 CCRP 1~255 0 Pe�iod CCRA Duty CCRP×�5� �553� ThePWMoutputperiodisdeterminedbytheCCRAregistervaluetogetherwiththeTMclock whilethePWMdutycycleisdefinedbythe(CCRP×256)exceptwhentheCCRPvalueisequalto 000b. |
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