AR0134CSSC00SUEAD datasheet(12/29 Pages) ONSEMI

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AR0134CS

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Single READ from Random Location

This sequence (Figure 8) starts with a dummy WRITE to

the 16-bit address that is to be used for the READ. The

master terminates the WRITE by generating a restart

condition. The master then sends the 8-bit read slave

address/data direction byte and clocks out one byte of

generating a no-acknowledge bit followed by a stop

condition. Figure 8 shows how the internal register address

maintained by the AR0134CS is loaded and incremented as

the sequence proceeds.

Figure 8. Single READ from Random Location

Previous Reg Address, N

Reg Address, M

M+1

Slave Ad-

dress

Reg

Address[15:8]

Reg

Address[7:0]

Slave Address

S = Start Condition

P = Stop Condition

Sr = Restart Condition

A = Acknowledge

A = No-acknowledge

Slave to Master

Master to Slave

Read Data

Single READ from Current Location

This sequence (Figure 9) performs a read using the

current value of the AR0134CS internal register address.

The master

terminates

the

READ

generating

a no-acknowledge bit followed by a stop condition.

The figure shows two independent READ sequences.

Figure 9. Single READ from Current Location

Previous Reg Address, N

Reg Address, N+1

N+2

Slave Address

Read Data

Slave Address

Read Data

Sequential READ, Start from Random Location

This sequence (Figure 10) starts in the same way as the

single READ from random location (Figure 8). Instead of

generating a no-acknowledge bit after the first byte of data

has been transferred, the master generates an acknowledge

bit and continues to perform byte READs until “L” bytes

have been read.

Figure 10. Sequential READ, Start from Random Location

Previous Reg Address, N

Reg Address, M

Slave Address

Reg Address[15:8]

M+1

Reg Address[7:0]

Read Data

Slave Address

M+L

M+L−1

M+L−2

M+1

M+2

M+3

Read Data

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