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LC823450 bảng dữ liệu(PDF) 91 Page - ON Semiconductor

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PLL1 (System)
The figure below shows the PLL1 circuit. Place the
decoupling capacitor in the terminal neighborhood on the
board, and keep low noise by apart from other power supply
lines.
Figure 40. PLL1 (System)
VCNT1
R1
C1
C2
+
C4
C3
R2
AVSSPLL1
AVDDPLL1
AVSSPLL1
AVDDPLL1
Table 56. PLL1 (SYSTEM)
Symbol
Value1 (Note 67)
Value2 (Note 68)
Serial Number or Accuracy
R1
100
Ω
100
Ω
±5%
R2
*M
Ω
*M
Ω
±5%
C1
4.7
μF
0.1
μF
capacitor
:±10%
temperature
:±15%
(
−20_C to +65_C )
C2
0.047
μF
0.001
μF
C3
0.1
μF
0.1
μF
C4
33
μF
33
μF
16CV33BS
66. C4: refers to the part of mounting on the catalog of our company (CV−B S Series).
67. appropriate value for Fref
≥ 32.768 kHz.
68. appropriate value for Fref
≥ 1 Mhz.
69. Use R2 basically by unmounting.
The characteristic of PLL might be improved by mounting R2. Prepare the wire pattern.
70. The values of parts are for reference. There is a possibility that the adjustment is needed according to the situation of the set.
71. Connect with decoupling capacitor in the terminal neighborhood on the board, and keep low noise by apart from other power supply lines.



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