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AT40K bảng dữ liệu(PDF) 36 Page - ATMEL Corporation

tên linh kiện AT40K
Giải thích chi tiết về linh kiện  5K - 50K Gates Coprocessor FPGA with FreeRAM
PDF  67 Pages
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nhà sản xuất  ATMEL [ATMEL Corporation]
Trang chủ  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT40K bảng dữ liệu(HTML) 36 Page - ATMEL Corporation

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36
AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
Notes:
1. CMOS buffer delays are measured from a V
IH of 1/2 VCC at the pad to the internal VIH at A. The input buffer load is constant.
2. Buffer delay is to a pad voltage of 1.5V with one output switching.
3. Parameter based on characterization and simulation; not tested in production.
4. Exact power calculation is available in Atmel FPGA Designer software.
AC Timing Characteristics – 3.3V Operation AT40KLV
Delays are based on fixed loads and are described in the notes.
Maximum times based on worst case: VCC = 3.0V, temperature = 70°C
Minimum times based on best case: VCC = 3.6V, temperature = 0°C
Cell Function
Parameter
Path
-3
Units
Notes
Async RAM
Write
tWECYC (Minimum)
cycle time
12.0
ns
Write
t
WEL (Minimum)
we
5.0
ns
Pulse width low
Write
t
WEH (Minimum)
we
5.0
ns
Pulse width high
Write
t
AWS (Minimum)
wr addr setup -> we
5.3
ns
Write
tAWH (Minimum)
wr addr hold -> we
0.0
ns
Write
tDS (Minimum)
din setup -> we
5.0
ns
Write
tDH (Minimum)
din hold -> we
0.0
ns
Write/Read
t
DD (Maximum)
din -> dout
8.7
ns
rd addr = wr addr
Read
t
AD (Maximum)
rd addr -> dout
6.3
ns
Read
t
OZX (Maximum)
oe -> dout
2.9
ns
Read
tOXZ (Maximum)
oe -> dout
3.5
ns
Sync RAM
Write
tCYC (Minimum)
cycle time
12.0
ns
Write
t
CLKL (Minimum)
clk
5.0
ns
Pulse width low
Write
t
CLKH (Minimum)
clk
5.0
ns
Pulse width high
Write
t
WCS(Minimum)
we setup -> clk
3.2
ns
Write
tWCH (Minimum)
we hold -> clk
0.0
ns
Write
tACS (Minimum)
wr addr setup -> clk
5.0
ns
Write
tACH (Minimum)
wr addr hold -> clk
0.0
ns
Write
tDCS (Minimum)
wr data setup -> clk
3.9
ns
Write
t
DCH (Minimum)
wr data hold -> clk
0.0
ns
Write/Read
t
CD (Maximum)
clk -> dout
5.8
ns
rd addr = wr addr
Read
tAD (Maximum)
rd addr -> dout
6.3
ns
Read
tOZX (Maximum)
oe -> dout
2.9
ns
Read
tOXZ (Maximum)
oe -> dout
3.5
ns



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