ADC31RF80IRMP datasheet(97/136 Pages) TI1

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ADC31RF80

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SBAS860 – AUGUST 2017

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8.5.9.3 Register 003h (address = 003h), JESD Digital Page

Figure 183. Register 003h

LINK LAYER TESTMODE

LINK LAY RPAT

LMFC MASK

RESET

JESD MODE1

JESD MODE2

RAMP 12BIT

R/W-0h

R/W-1h

R/W-0h

Table 72. Register 003h Field Descriptions

Bit

Field

Type

Reset

Description

7-5

LINK LAYER TESTMODE

R/W

These bits generate a pattern according to section 5.3.3.8.2 of

the JESD204B document.

000 = Normal ADC data

001 = D21.5 (high-frequency jitter pattern)

010 = K28.5 (mixed-frequency jitter pattern)

011 = Repeat initial lane alignment (generates a K28.5 character

and repeats lane alignment sequences continuously)

100 = 12-octet RPAT jitter pattern

LINK LAY RPAT

R/W

This bit changes the running disparity in a modified RPAT

pattern test mode (only when link layer test mode = 100).

0 = Normal operation

1 = Changes disparity

LMFC MASK RESET

R/W

0 = Normal operation

JESD MODE1

R/W

These bits select the configuration register to configure the

correct LMFS frame assemblies for different decimation settings;

see the JESD frame assembly tables in the JESD204B Frame

Assembly section

JESD MODE2

R/W

These bits select the configuration register to configure the

correct LMFS frame assemblies for different decimation settings;

see the JESD frame assembly tables in the JESD204B Frame

Assembly section

RAMP 12BIT

R/W

12-bit RAMP test pattern.

0 = Normal data output

1 = Digital output is the RAMP pattern

8.5.9.4 Register 004h (address = 004h), JESD Digital Page

Figure 184. Register 004h

REL ILA SEQ

W-0h

R/W-0h

Table 73. Register 004h Field Descriptions

Bit

Field

Type

Reset

Description

7-2

Must write 0

1-0

REL ILA SEQ

R/W

These bits delay the generation of the lane alignment sequence

by 0, 1, 2, or 3 multiframes after the code group synchronization.

00 = 0 multiframe delays

01 = 1 multiframe delay

10 = 2 multiframe delays

11 = 3 multiframe delays

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