ADC31RF80IRMP datasheet(33/136 Pages) TI1

33 / 136 page

Input Clock

Divider

(Divide-by-4)

ASSERT SYSREF REG

(In Master Page)

SEL SYSREF REG

(In Master Page)

CLKIN

(CLKP-CLKM)

SYSREF

(SYSREFP-SYSREFM)

DLL

NCO,

JESD Interface

(LMFC Counter)

MASK CLKDIV SYSREF

(In JESD Digital Page)

MASK NCO SYSREF

(In JESD Digital Page)

PDN SYSREF

(In Master Page)

ADC31RF80

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SBAS860 – AUGUST 2017

Product Folder Links: ADC31RF80

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Feature Description (continued)

8.3.3.1 Using SYSREF

The ADC31RF80 uses SYSREF information to reset the clock divider, the NCO phase, and the LMFC counter of

the JESD interface. The device provides flexibility to provide SYSREF information either from dedicated pins or

through SPI register bits. SYSREF is asserted by a low-to-high transition on the SYSREF pins or a 0-to-1 change

in the ASSERT SYSREF REG bit, as shown in Figure 90, when using SPI registers.

Figure 90. Using SYSREF to Reset the Clock Divider, the NCO, and the LMFC Counter

The ADC31RF80 samples the SYSREF signal on the input clock rising edge. Required setup and hold time are

listed in the Timing Requirements table. The input clock divider gets reset each time that SYSREF is asserted,

as shown in Table 1, whereas the NCO phase and the LMFC counter of the JESD interface are reset on each

SYSREF assertion after disregarding the first two assertions.

Table 1. Asserting SYSREF

SYSREF ASSERTION INDEX

ACTION

INPUT CLOCK DIVIDER

NCO PHASE

LMFC COUNTER

Gets reset

Does not get reset

Gets reset

Does not get reset

Gets reset

4 and onwards

Gets reset

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