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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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ADC31RF80IRMP bảng dữ liệu(PDF) 32 Page - Texas Instruments |
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ADC31RF80IRMP bảng dữ liệu(HTML) 32 Page - Texas Instruments |
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32 / 136 page  V CM 50 50 CLKINP 100 SYSREFP SYSREF Capture Delay CLKINM SYSREFM Clock Amplitude (vPP) 0.2 1 2 50 100 150 200 250 300 350 D061 fIN = 1 GHz fIN = 2 GHz 32 ADC31RF80 SBAS860 – AUGUST 2017 www.ti.com Product Folder Links: ADC31RF80 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Feature Description (continued) The analog-to-digital converter (ADC) aperture jitter is a function of the clock amplitude applied to the pins. Figure 88 shows the equivalent aperture jitter for input frequencies at a 1-GHz and a 2-GHz input. Depending on the clock frequency, a matching circuit can be designed in order to maximize the clock amplitude. Figure 88. Equivalent Aperture Jitter vs Input Clock Amplitude 8.3.3 SYSREF Input The SYSREF signal is a periodic signal that is sampled by the ADC31RF80 device clock and is used to align the boundary of the local multiframe clock inside the data converter. SYSREF is also used to reset critical blocks [such as the clock divider for the interleaved ADCs, numerically-controlled oscillators (NCOs), decimation filters and so forth]. The SYSREF input requires external biasing. Furthermore, SYSREF must be established before the SPI registers are programmed. A programmable delay on the SYSREF input, as shown in Figure 89, is available to help with skew adjustment when the sampling clock and SYSREF are not provided from the same source. Figure 89. SYSREF Internal Circuit Diagram |
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