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RT3607CE bảng dữ liệu(PDF) 4 Page - Richtek Technology Corporation |
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RT3607CE bảng dữ liệu(HTML) 4 Page - Richtek Technology Corporation |
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4 / 69 page  4 RT3607CE www.richtek.com DS3607CE-01 June 2016 © Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Functional Block Diagram Loop Control Protection Logic SVID Interface Configuration Registers Control Logic UVLO VREF GND FB COMP RGND PWM4 ISEN4N Soft-Start & Slew Rate Control VSET_M ERROR AMP From Control Logic Offset Cancellation ISEN4P ISEN3N ISEN3P ISEN2N ISEN2P ISEN1N ISEN1P Current Balance + - + - DAC TON GEN/ Driver Interface + - + - + - + - Current Mirror IC1_M Current Mirror Current Mirror Current Mirror + - OCS_M IMON PWM CMP + - + RSET_M TONSET IMON Filter IMONI_M 1/3 DVID SR DVIDTH_M DVIDWIDTH_M IB1_M IC2_M IB2_M IC3_M IB3_M IC4_M IB4_M GM VREF OCS_TH_M QRTH_M QRWIDTH_M IB1_M IB2_M IB3_M IB4_M PS_M PWM3 PWM2 PWM1 FBA COMPA RGNDA Soft-Start & Slew Rate Control VSET_A ERROR AMP From Control Logic Offset Cancellation ISENA3N ISENA3P ISENA2N ISENA2P ISENA1N ISENA1P Current Balance + - + - DAC TON GEN/ Driver Interface + - + - + - Current Mirror IC1_A Current Mirror Current Mirror + - OCS_A IMONA PWM CMP + - + RSET_A TONSETA IMON Filter IMONI_A 1/3 DVID SR DVIDTH_A DVIDWIDTH_A IB1_A IC2_A IB2_A IC3_A IB3_A GM VREFI OCS_TH_A QRTH_A QRWIDTH_A IB1_A IB2_A IB3_A PS_A PWMA3 PWMA2 PWMA1 + - OV_X/NV_X/ OC_PER_X/OC_SUM_X IC1_M IC2_M IC3_M IC4_M IC1_A IC2_A IC3_A OCS_M OCS_A PS_M PS_A VID_M VID_A ADC MUX ADC MUX DAC DVIDTH_X DVIDWIDTH_X QR_X QRWIDTH_X OCS_TH_X RSET_X ICCMAX_X OCP_PER_X + - Current Mirror IBIASI 2V IBIAS VR address H/L FSW ramp DVID SR Disable DVID compensation Decrease GTU/SA ramp (only in 1-phase) Zero load-line Anti-OVS Anti-OVS behavior AI gain PSYS function Anti-OVS behavior Anti-OVS |
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