CS43199 datasheet(76/111 Pages) CIRRUS

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DS1113F1

CS4399

7.2 PLL Registers

7.2.2

PLL Setting 2

Address 0x30002

R/W

76543210

PLL_DIV_FRAC_0

Default

00000000

Bits

Name

Description

7:0

PLL_DIV_

FRAC_0

PLL fractional portion of divide ratio LSB. There are 3 bytes of PLL feedback divider fraction portion and this is LSB byte;

e.g., 0xFF means (2-17 + 2-18 + …+2-24).

0000 0000 (Default)

7.2.3

PLL Setting 3

Address 0x30003

R/W

76543210

PLL_DIV_FRAC_1

Default

00000000

Bits

Name

Description

7:0

PLL_DIV_

FRAC_1

PLL fractional portion of divide ratio middle byte; e.g., 0xFF means (2-9 + 2-10 + …+2-16).

0000 0000 (Default)

7.2.4

PLL Setting 4

Address 0x30004

R/W

76543210

PLL_DIV_FRAC_2

Default

00000000

Bits

Name

Description

7:0

PLL_DIV_

FRAC_2

PLL fractional portion of divide ratio MSB; e.g., 0xFF means (2-1 + 2-2 + …+2-8).

0000 0000 (Default)

7.2.5

PLL Setting 5

Address 0x30005

R/W

76543210

PLL_DIV_INT

Default

01000000

Bits

Name

Description

7:0 PLL_DIV_INT PLL integer portion of divide ratio. Integer portion of PLL feedback divider.

0100 0000 (Default)

7.2.6

PLL Setting 6

Address 0x30008

R/W

76543210

PLL_OUT_DIV

Default

00010000

Bits

Name

Description

7:0

PLL_OUT_

DIV

Final PLL clock output divide value.

0001 0000 (Default)

7.2.7

PLL Setting 7

Address 0x3000A

R/W

76543210

PLL_CAL_RATIO

Default

10000000

Bits

Name

Description

7:0

PLL_CAL_

RATIO

PLL calibration ratio. See Section 4.6.2 for configuration details. Target value for PLL VCO calibration.

1000 0000 (Default)

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